1. Field of the Invention
The present invention relates to a process for the formation of resist patterns, particularly negative resist patterns. The pattern formation process of the present invention can be effectively used in both a single layer resist process and a two layer resist process currently used to obtain resist patterns having a high resolution and aspect ratio on a substrate having topographic features. The resulting resist patterns can be advantageously used in the production of semiconductor devices such as large-scale integrated (LSI) circuits, very-large-scale integrated (VLSI) circuits, and bubble memory devices, and the like.
2. Description of the Related Art
As is well-known, a thin layer formation technology and lithography are widely utilized in the production of LSI, VLSI, and the like, for example. An important process in this technology is a resist process used in the field of fine fabrication. Generally, the resist process is classified into a single layer resist process and a multilayer resist process, such as a two layer or three layer resist process. In these resist processes, a plurality of negative-working or positive-working resist materials are used depending upon the desired results and other factors.
For example, the single layer resist process using a negative-working resist material is conducted as follows: A solution of the selected resist material is coated on a substrate and then dried to form a resist layer. The resist layer is patterned by exposure to light or radiation to which the resist material is sensitive, for example, ultraviolet radiation. As a result of this exposure, the resist material in an exposed area of the resist layer is insolubilized in a developing solution such as organic solvents. The mechanism of insolubilization is based on, for example, cross-linking of the resist material. The exposed resist layer is developed with the developing solution to remove the unexposed resist material from the resist layer, and a negative resist pattern is thus formed on the substrate. This process has a drawback, however, in that a high quality resist pattern cannot be obtained, since the substrate is swollen as a result of contact thereof with the solvent used as the developer in the wet development step.
To remove the above drawback due to wet development, the inventor created an improved resist process as disclosed in Japanese Unexamined Patent Publication (Kokai) No. 63-15240, in which the resist process or patterning process comprises coating a resist material having a polymer having a double bond or triple bond in a backbone chain thereof, as a main component, on a substrate to form a layer of the resist material, exposing a selected area of the layer to ultraviolet radiation, X-rays or electron beams, and developing the exposed layer with the down flow etching method using an oxygen-containing gas. The polymer includes, for example, 1,4-polybutadiene, 1,4-polybutadiyne or derivatives thereof, and contains one or more benzene rings and chlorine atoms in a polymeric structure thereof. Further, the oxygen-containing gas used in the development step is, for example, a mixture of oxygen and carbon tetrafluoride. According to the process of Japanese Kokai 63-15240, since specific polymers containing unsaturated bonds as well as benzene rings and chlorine atoms are used as the resist material and the exposed resist material is developed with a dry process, high quality negative resist patterns can be obtained.
The substrate used in the production of the semiconductor devices and the like, as is well-known in the art, may comprise any material such as a semiconductor, for example, silicon (Si). The substrate may have any layer such as an insulating layer, for example, SiO.sub.2 layer or a polysilicon layer on a surface thereof, and further, may contain topographic features, i.e., concaves and convexes, on a surface thereof. The topographic features are produced, for example, when an electrically insulating layer is coated over the surface of the circuit pattern-bearing substrate, and the topographic features have a height of about 1 to 2 .mu.m.
When the substrate to be processed has topographic features, it is difficult to use the above-described single layer resist process to obtain resist patterns of a submicron order on the substrate, because the topographic features adversely affect the resulting resist patterns. Namely, due to a disordered reflection of exposure light or radiation such as electron beams at the concaves and convexes in the resist patterns, the formation of fine resist patterns at a high accuracy is impossible.
In place of the single layer resist process, a multilayer resist process, especially a two layer resist process has been used to obtain fine resist patterns of a submicron order on the topographic features-bearing substrate. The two layer resist process generally comprises coating an organic resist material such as phenol-novolac resin or cresol-novolac resin on the substrate to level the topographic features thereof. The resulting resist layer (hereinafter "lower resist layer") is relatively thick and has a thickness of about 2 to 3 .mu.m, for example. After formation of the lower resist layer, a polymeric resist material having a high resistance to dry etching, such as chloromethylated polydiphenyl siloxane of the structure formula: ##STR1## wherein m represents a polymerization degree ("SNR" commercially available from Tosoh Corporation) or a copolymer of trimethylsilylstyrene and chloromethyl styrene of the structural formula: ##STR2## is coated on the lower resist layer. The resulting layer (hereinafter "upper resist layer") is remarkably thinner than the lower resist layer and generally has a thickness of about 0.2 to 0.5 .mu.m. The reason why the silicon-containing polymers are suitable as the upper resist material is that these polymers also can form an SiO.sub.x layer having a high resistance to dry etching during the subsequent O.sub.2 -RIE (reactive ion etching) generally used to transfer a pattern of the upper resist layer to the lower resist layer.
After a two layer resist structure is produced, a pattern formation is conducted as follows: The upper resist layer is patterned by exposure to light or radiation, for example, by applying a projection exposure or contact exposure, through a mask, to the resist layer. When the resist layer is negative-working, an exposed area of the layer is insolubilized in a developing solution. The exposed upper resist layer is then developed with the developing solution to remove an unexposed area thereof, and a pattern of the upper resist layer is thus formed. Using this pattern as a mask, the underlying lower resist layer is dry etched with, for example, O.sub.2 -RIE, to transfer the pattern of the upper resist layer to the lower resist layer, and a desired negative resist pattern is finally obtained.
The above process can overcome the problems of the topographic features, but since it is based on a solution development system, the same problem as in the above-described single layer resist arises, i.e., swelling of the upper resist layer. To remove this swelling problem, it has been proposed to develop the upper resist layer under dry conditions. For example, Japanese Unexamined Patent Publication (Kokai) No. 58-165321 teaches dry plasma development of the silicon-containing upper resist layer using plasma containing a gas of halogen compounds.
More particularly, Example 1 of Japanese Kokai 58-165321 discloses spin-coating polyimide on a silicon wafer to form a lower resist layer having a thickness of 1 .mu.m. The lower resist layer is then coated with a mixture (5:1) of polyglycidyl methacrylate and dimethyldiphenylsilane to form an upper resist layer having a thickness of 0.2 .mu.m. The resulting resist structure is pattern-wise exposed to electron beams, and then developed using a plasma of oxygen gas and Freon.RTM. gas. The unexposed area of the upper resist layer is thus removed. Next, the resist structure is dry etched. When the patterned upper resist layer containing Si is brought into contact with oxygen plasma during dry etching of the lower resist layer, SiO.sub.2 is produced in the upper resist layer, which then becomes hard. As a result, a retention rate of the resist, i.e., ratio (%) of the thickness of the resist after development to that of the resist before development in the same area of the resist layer where the resist should be retained, can be improved.
Nevertheless, the prior art two layer resist process has a disadvantage in that a retention rate of the resist in the resulting resist patterns is not satisfactory because physical actions such as ion bombardment during the O.sub.2 -RIE adversely affect the improvement of such retention rate. Further, if the silicon-containing resist or polymer is prepared by introducing a silicon atom into the organic resist or polymer, an amount of the silicon in the resulting upper resist patterns is limited and, in practice, is not high enough to ensure a satisfactory resistance to the O.sub.2 -RIE of the upper resist layer during etching of the lower resist layer. It is, therefore, desired to provide an improved process for the resist pattern formation which ensures a formation of fine resist patterns of a submicron order at a high resolution and retention rate of the resist. It is also desired to confer a high resistance to dry etching such as the O.sub.2 -RIE to the resulting resist pattern.